1. Field of the Invention
The present invention relates to a display array, and more particularly to a pixel array.
2. Description of the Prior Art
Generally, a flat display device primarily includes a display panel and a plurality of driver ICs. The display panel includes a pixel array, and the pixels of the pixel array are driven by corresponding scan lines and corresponding data lines. In order to popularize the flat display device, industries have spent a great amount of effort in reducing the manufacturing costs. In recent years, a new half source driver design layout was developed which reduces the number of data driver ICs required through primarily changing the layout of the pixel array.
FIG. 1A is a schematic diagram of a conventional pixel array. Referring to FIG. 1A, in the design of the conventional pixel array 100a, the two scan lines 120a are disposed between pixels 130a, 130b of two the adjacent rows, wherein the gate electrodes 142, 152 of the active components 140, 150 of the two pixels 130a, 130b are respectively disposed on two sides of the scan lines 120a. In the manufacturing process of the active component 140, 150, the gate electrodes 142, 152 of the active components 140, 150, and the source electrodes 144, 154 and the drain electrodes 146, 156 of the active components 140, 150 are manufactured though the use of different photo masks. For example, the gate electrodes 142, 152 of the active components 140, 150 come out of the first photo mask process and the source electrodes 144, 154 and the drain electrodes 146, 156 of the active components 140, 150 come out of the fourth photo mask process. These two processes should be aligned with precise accuracy, and if the photo mask machine is misaligned from the previous process, misalignment would occur between the gate electrodes 142, 152, the source electrodes 144, 154 and the drain electrodes 146, 156 of the active components 140, 150, forcing the characteristics of the active components 140, 150 to deviate from the original design purpose values. Meanwhile, since the gate electrodes 142, 152 correspond to the two sides of the scan lines 120 respectively, when the gate electrodes 142, 152 and the drain electrodes 146, 156 of the active components 140, 150 are misaligned, the areas where the gate electrodes 142, 152 and the drain electrodes 146, 156 of the active components 140, 150 of the pixels 130a, 130b overlap would vary in behaviors. If the deviation shifts towards the pixel 130b, a gate-drain parasitic capacitance Cgd of the pixel 130a on one side of the scan lines 120a will increase, while the gate-drain parasitic capacitance Cgd of the pixel 130b on the other side of the scan lines 120a will decrease, so that the gate-drain parasitic capacitances Cgd of the pixels 130a, 130b would be different. As a result, since the gate-drain parasitic capacitance Cgd differences induced by the process misalignment described above are significant, the color brightness disequilibrium uneven display brightness on the pixel array 100a during display would occur.
In order to minimize the difference of the gate-drain parasitic capacitance Cgd between the pixels, U.S. Pat. No. 6,583,777 provides a pixel array structure. Referring to FIG. 1B, a pixel array 100b includes a plurality of irregularly-arranged pixels R, G, B, and scan lines 110b and data lines 120b connected to the pixels R, G, B respectively. The scan line 110b extends linearly along a row direction, and the data line 120b extends linearly along a column direction. The data line 120 intersects with the scan lines 110b perpendicularly. However, since the pixels R, G, B are irregularly-arranged, the color performance during the display is usually insufficient. Furthermore, since each of the pixels R, G, B crosses three scan lines 110b, such pixel array design would decrease the aperture ratio, resulting in insufficient brightness during the display and poor display quality.